The present invention relates to shift registers and, more particularly, to shift registers which accept parallel data and provide that same data in serial form at an output thereof.
Shift registers are well known and extensively used in many kinds of logic systems. Shift registers, formed as a cascade of a selected number of single logic value storage elements or storage registers, perform a number of different kinds of functions in such logic systems.
Thus, shift registers can be connected to serve as counters, logic wave form generators and many other kinds of logic subsystems where temporary storage of logic states are needed. One particularly useful function for shift registers is the performance of serial-to-parallel conversions and the opposite kinds of conversions, parallel-to-serial conversions, of multiple logic values.
In a parallel-to-serial converter, a plurality of logic values are concurrently provided to and stored in corresponding ones of the series-connected cascade of storage registers in the shift register. Subsequently, the contents of the storage registers are shifted along the series thereof so that each stored logic value sequentially appears at the output of the last storage register.
In these circumstances, a counter is needed to be provided which counts these shifts of the logic values, originally introduced in parallel into the storage registers, down the storage register cascade. When the number counted on such a counter has reached a value equal to the number of logic values which were originally introduced in parallel, an indication is available that the shifting has been completed in the shift register. Then, another set of logic values can be concurrently provided thereto for storage therein to again be converted to a serial stream.
This requirement of an accompanying counter increases the area of a monolithic integrated circuit chip devoted to the serial-to-parallel conversion process beyond that just required for the shift register to be provided therein. In addition, the size of the counter must increase as the length of the sift register increases. Thus, there is a desire to provide a shift register arrangement in which the need for an accompanying counter can be avoided.